A variety of techniques have been developed to increase the overall processing speed of computer systems. Vast improvements in integrated circuit processing technologies have contributed to the ability to increase computer processing speeds and memory capacity, thereby contributing to the overall improved performance of computer systems. The ability to produce integrated circuits with deep sub-micron features enables the density of electrical components, such as capacitors to also increase.
Dynamic random access memory (DRAM) chips, comprised of large arrays of capacitors with sub-micron features, are utilized for main memory in computer systems. DRAM is typically inexpensive and high density, thereby enabling large amounts of DRAM to be integrated per device. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). Increasing DDR DRAM device density and improving the overall technology of the DDR DRAM device within a computer system increases the speed of the DDR DRAM device; however, the higher speeds are more sensitive to voltage and temperature variation. Without periodic retraining, the voltage and temperature variations cause the data (DQ) timing parameters to fall out of tolerance limits, and thereby cause data errors.
Currently, in order to address these issues, a system may simply access a DDR DRAM device at lower speeds than the specified maximum speed without retraining. Operating at lower speeds reduces the system performance and is generally undesirable. Other changes used to avoid or mitigate training of the data timing parameters negatively affect power and performance of the system on chip (SOC) and/or significantly increase the cost of the platform of the SOC.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.